Following Moore's law and current scaling trends suggests that handling power dissipation in microprocessors is gradually becoming impractical, stressing the need for circuit designs that reduce active and leakage power. Additionally, global interconnects can be a limiting factor for performance since interconnect delay increases quadratically with increase in the length of the wire. Both voltage-mode techniques and current-mode techniques have been used to reduce this trend in interconnect delay. However, the power dissipation due to interconnect circuitry such as repeaters can significantly increase the power dissipation of a chip, at least in part due to the static power dissipation of such circuits.
A differential current sense amplifier (DCSA), can be applied to global interconnects. Such a circuit provides current-mode signaling, which, unlike voltage-mode signaling, provides a low impedance termination at the receiver. FIG. 1 illustrates such a DCSA circuit, 100. In DCSA 100, the drains of transistors 102 and 104 are used for low impedance termination. This termination effectively clamps the interconnect at a specified voltage. Standard inverter based drivers provide the current push or pull to the voltage clamped interconnect wires. Two interconnect wires connect the signal and its complement to either input on the differential current sense amplifier (DCSA). A cross coupled inverter pair is formed by transistors 106, 108, 110, and 112. During an equalizing phase these cross coupled inverters are held at meta stable state by an NMOS device 114. The evaluation phase begins once the equalizing signal, EQ is turned off. In this phase, small current differences will force the cross coupled inverters out of the meta stable state. Positive feedback amplifies the input signals and gives nearly full scale voltages at the outputs. In general this approach is faster than voltage-mode repeater based interconnects, and performs especially well in highly capacitive wires.